1. Technical Field of the Invention
The present invention relates to the field of integrated circuit, and more particularly to three-dimensional memory (3D-M).
2. Prior Art
Three-dimensional memory (3D-M) is a monolithic semiconductor memory comprising a plurality of vertically stacked memory levels. It includes three-dimensional read-only memory (3D-ROM) and three-dimensional random-access memory (3D-RAM). The 3D-ROM can be further categorized into three-dimensional mask-programmed read-only memory (3D-MPROM) and three-dimensional electrically-programmable read-only memory (3D-EPROM). 3D-M may further comprise at least one of a memristor, a resistive random-access memory (RRAM or ReRAM), a phase-change memory, a programmable metallization cell (PMC), a conductive-bridging random-access memory (CBRAM) or other memory devices.
U.S. Pat. No. 5,835,396 issued to Zhang on Nov. 3, 1998 discloses a 3D-M, more particularly a 3D-ROM (FIG. 1A). It comprises a substrate 0 and a substrate circuit 0K located thereon. An insulating dielectric 0d covers the substrate circuit 0K and is planarized. A first memory level 10 is stacked above the insulating dielectric 0d, with a second memory level 20 stacked above the first memory level 10. The first and second memory levels 10, 20 are coupled to the substrate circuit 0K through contact vias 13a, 23a, respectively. Each of the memory levels (e.g. 10, 20) comprises a plurality of upper address-lines (i.e. y-lines, e.g. 12a-12d, 22a-22d), a plurality of lower address-lines (i.e. x-lines, e.g. 11a, 21a) and a plurality of memory devices (e.g. 1aa-1ad, 2aa-2ad) at the intersections between the upper and lower address-lines.
Each memory level (e.g. 20) comprises at least a memory array (e.g. 200A). A memory array 200A is a collection of memory devices (e.g. 2aa-2ad) in a memory level 20 that share at least one address-line (e.g. 21a, 22a-22d). Within a single memory array 200A, all address-lines (e.g. 21a, 22a-22d) are continuous; between adjacent memory arrays, address-lines are not continuous. On the other hand, a 3D-M die comprises a plurality of memory blocks (e.g. 100). The structure shown in FIG. 1A is a portion of the memory block 100. The topmost memory level 20 of the memory block 100 comprises only a single memory array 200A. In other words, within the topmost memory level 20 of the memory block 100, all address-lines 21a, 22a-22d are continuous and terminate at or near the edge of the memory block 100.
Each memory device 1aa is a two-terminal device having at least two possible states. Most common memory devices comprise diodes or diode-like devices. To be more specific, the memory cell 1aa comprises a diode layer whose electrical characteristic is that of a diode and a programmable layer whose state can be altered during or after manufacturing (FIG. 1A). Alternatively, the diode layer and the programmable layer in the memory device 1aa can be merged into a single layer, as disclosed in U.S. Pat. No. 8,071,192 issued to Lu et al. The memory device 1aa is represented by a symbol combining a diode and a capacitor in FIG. 1B. Because the memory devices 1aa . . . are formed at the cross-points of address-lines 12a, 11a . . . , the memory array 100A is a cross-point array.
Throughout the present invention, a diode is broadly interpreted as any two-terminal device whose resistance at the read voltage is substantially lower than when the applied voltage has a magnitude smaller than or polarity opposite to that of the read voltage. It is also referred to as quasi-conduction layer in Zhang (U.S. Pat. No. 5,835,396). In one exemplary embodiment, the diode is a semiconductor diode, e.g. p-i-n silicon diode, as disclosed in Crowley et al. “512 Mb PROM with 8 Layers of Antifuse/Diode Cells” (referring to 2003 International Solid-State Circuits Conference, FIG. 16.4.1). In another exemplary embodiment, the diode is a metal-oxide diode, e.g. titanium oxide, nickel oxide, as disclosed in Chevallier et al. “A 0.13 um 64 Mb Multi-Layered Conductive Metal-Oxide Memory” (referring to 2010 International Solid-State Circuits Conference, FIG. 14.3.1). Although the metal oxide layer in Chevallier has a nearly symmetric I-V characteristic (i.e. the metal oxide layer is conductive in both polarities), it is still considered as a diode because its I-V characteristic is logarithmic.
The substrate circuit 0K comprises first and second decoders 14, 24 for the first and second memory levels 10, 20, respectively. Each of the first and second decoders 14, 24 comprises a plurality of decoding devices. Decoding device is the basic building block of the decoders 14, 24. It performs at least a portion of the decoding function for the memory array. The decoding device has a conduction mode and a blocking mode: in the conduction mode, current conduction is allowed in an address-line associated with the decoding device; in the blocking mode, current conduction is blocked in this address-line. Most common decoding devices are transistors or transistor-like devices, which have three or more terminals. In a parent application of the present application (i.e. Application Ser. No. 14/636,346), the decoding devices are also referred to as switching devices.
As is well known in the art, the manufacturing process of a diode is much simpler than that of a transistor. To lower the overall manufacturing cost of a conventional 3D-M, only memory devices (i.e. diodes or diode-like devices), but no decoding devices (i.e. transistors or transistor-like devices), are formed in each memory level 10. Because no decoding is performed in any memory levels 10, 20 (i.e. all decodings are performed in the substrate circuit 0K), each address-line 11a has to have its own contact via 13a to the substrate circuit 0K. In other words, the contact via 13a cannot be shared between address-lines. As a result, the contact vias (e.g. 13a, 13c) at most have a pitch pc twice as large as the x-line pitch p, i.e. pc=2p (FIG. 1C). This happens when the contact vias (e.g. 13a, 13c) are interleaved, i.e. the x-lines (e.g. 11a, 11c) have their contact vias (e.g. 13a, 13c) formed to their right end (+x direction), while their immediately neighboring x-lines (e.g. 11b, 11d) have their contact vias (not shown) formed to their left end (−x direction). Hereinafter, a pitch is the center-to-center distance between two adjacent contact vias (or, two adjacent lines). In most cases, the line pitch p is twice the line width f (i.e. p=2f). Apparently, the contact-via size dc and spacing gc could be twice the x-line width f (i.e. dc=2f, gc=2f) (FIG. 1D). Even so, because the line width f can be made half of the minimum lithography resolution F (i.e. f=F/2) or even smaller, the contact-via size is still the minimum lithography resolution F (i.e. dc=F, gc=F). Because they need a high-resolution (F-node) mask, the contact vias incur a high manufacturing cost.
In the present invention, all contact vias associated with a single memory level are collectively referred to as a contact-via set (FIG. 1E). For example, all contact vias (e.g. 13a-13z) associated with the memory level 10 form a first contact-via set 13, and all contact vias (e.g. 23a-23z) associated with the memory level 20 form a second contact-via set 23. Because each memory level has its own contact-via set (FIG. 1A), a 3D-M with a large number of memory levels needs a large number of contact-via sets. This further increases the manufacturing cost.
With a small spacing (gc=2f), the contact vias (e.g. 13a, 13c, 13e) are dense contact vias. They fence the substrate circuit 0K in such a way that the interconnect of the substrate circuit 0K cannot pass through the gaps 04g between the contact vias 13a, 13c . . . (FIG. 1D). This severely limits the design flexibility of the substrate circuit 0K. Because the dense contact vias completely separate the first and second decoders 14, 24, the second decoder 24 cannot share any components with the first decoder 14 and needs to be a full decoder (FIG. 1E). This requires the x-line 21a on the memory level 20 to extend an excessive distance Lpx to reach the contact vias 23a (FIG. 1A). Long Lpx lowers the array efficiency and reduces the memory density. More details will be disclosed in the following paragraphs.
The excessive distance Lpx extended by the x-line 21a is referred to as the x-peripheral length. It is defined as the length of the x-line 21a from the last memory device 2ad of the memory array 200A to the edge of the x-line 21a or the contact via 23a, whichever is longer (FIG. 1A). Because the topmost memory level 20 has the longest x-line and defines the footprint of the memory block 100, Lpx only needs to be defined for the topmost memory level 20. Likewise, a y-peripheral length Lpy can be defined. For a memory array 200A containing N*N memory devices, the useful length Lm of the x-line 21a (i.e. the length used for the memory devices) is N*p, with its total length Lt=N*p+2Lpx. Accordingly, the x-efficiency Ex, which is the percentage of the x-line 21a used for memory devices, can be expressed as Ex=Lm/Lt=(1+2Lpx/N/p)−1; and the array efficiency EA, which is the percentage of the memory array 200A used for memory devices, is a product of Ex and Ey (y-efficiency), i.e. EA=Ex*Ey=(1+2Lpx/N/p)−1(1+2Lpy/N/p)−1.
To accommodate a full decoder 24 between the contact vias 13a and 23a on the substrate 0, the x-line 21a of the memory level 20 has to be extended by at least a full width WD of the decoder 24, i.e. Lpx>WD (FIGS. 1A & 1E). Likewise, the y-line 22a also needs to be extended by an excessive distance. Large peripheral lengths Lpx and Lpy increase the memory-array size, lower the array efficiency and reduces the memory density.
Besides the above adverse effects, dense contact vias cast a shadow on the future of three-dimensional integrated circuit (3D-IC). In the post Moore's Law era, 3D-IC is a natural extension of the conventional two-dimensional integrated circuit (2D-IC). 3D-M is considered as a most suitable candidate for the 3D-IC because its memory levels do not occupy any substrate and its substrate can be used to form circuit components such as a processor. One possible 3D-IC is a 3D-M-based system-on-a-chip (SoC). However, as dense contact vias partition the substrate into isolated regions, the layout of the substrate circuit become difficult if not impossible.